Field
Embodiments of the present disclosure generally relate to integrated circuit fabrication methods, and in particular, to correcting seam defects in semiconductor devices.
Description of the Related Art
The miniaturization of semiconductor devices continues to require increasing complexity of geometry and arrangement of material layers which form the device. Among these, properly filling features formed on the semiconductor device, such as trenches and vias, with a material is increasingly difficult due to the shrinking size of the features.
Features are typically filled by a deposition process, such chemical vapor deposition (CVD), physical vapor deposition (PVD), or plating processes, which can result in less than optimal filling of the features. Problems arise from the accumulation of material at the upper surface of the feature. The accumulation of such material at the edges of the feature can block or otherwise obstruct the feature prior to completely and evenly filling the feature, resulting in the formation of voids, seams, and uneven structures within the feature. The smaller features that are used in smaller geometry devices, such as trenches in the tens-of-nanometer range, necessarily have a larger aspect ratio (i.e., relationship of feature height to width) than do larger geometry devices, thereby exacerbating the trench and via filling difficulties described above.
Conventional approaches utilize multiple cycles of deposition and anneal in attempt to repair seams and cavities in the features. However, these conventional approaches result in extremely slow process time. Further, these approaches can damage the material of the semiconductor device and cause reliability issues in the operation of the semiconductor device.
Therefore, there is a need for an improved method of correcting seam defects.